JNTU-H B.TECH R-19 III Year-I Semester Syllabus For Digital system design using hdl PDF 2022
February 5, 2022 2022-02-05 17:47JNTU-H B.TECH R-19 III Year-I Semester Syllabus For Digital system design using hdl PDF 2022
JNTU-H B.TECH R-19 III Year-I Semester Syllabus For Digital system design using hdl PDF 2022
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You will be able to find information about Digital system design using hdl along with its Course Objectives and Course outcomes and also a list of textbook and reference books in this blog.You will get to learn a lot of new stuff and resolve a lot of questions you may have regarding Digital system design using hdl after reading this blog. Digital system design using hdl has 5 units altogether and you will be able to find notes for every unit on the CynoHub app. Digital system design using hdl can be learnt easily as long as you have a well planned study schedule and practice all the previous question papers, which are also available on the CynoHub app.
All of the Topic and subtopics related to Digital system design using hdl are mentioned below in detail. If you are having a hard time understanding Digital system design using hdl or any other Engineering Subject of any semester or year then please watch the video lectures on the official CynoHub app as it has detailed explanations of each and every topic making your engineering experience easy and fun.
Digital system design using hdl Unit One
UNIT ONE
Hardware Description Languages, FPGA Boards and Software Tools.
Field-Programmable Gate Arrays: Transistor as a Switch, Logic Gates from Switches, FPGA Building Blocks, Layout of the Xilinx Artix-7 XC7A35T FPGA, Input/output Blocks, Configurable Logic Blocks, Interconnect Resources, Block RAM, DSP Slices, Clock Management, The XADC Block, High-Speed Serial I/O Transceivers, Peripheral Component Interconnect Express Interface, FPGA-Based Digital System Design Philosophy, How to Think While Using FPGAs, Advantages and Disadvantages of FPGAs, Usage Areas of FPGAs
Verilog Fundamentals, Module Representation, Timing and Delays in Modelling, Hierarchical Module Representation, Testbench Formation in Verilog, Structure of a Verilog Testbench File, Displaying Test Results.
Digital system design using hdl Unit Two
VERILOG DATA TYPES AND OPERATORS
Data Types in Verilog, Net and Variable Data Types, Data Values, Naming a Net or Variable, Defining Constants and Parameters, Defining Vectors, Operators in Verilog, Arithmetic Operators, Concatenation and Replication Operators, Application on Data Types and Operators, FPGA Building Blocks Used in Data Types and Operators, Implementation Details of Vector Operations, Implementation Details of Arithmetic Operations.
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Digital system design using hdl Unit Three
UNIT THREE
Combinational Circuit Analysis, Logic Function Formation between Input and Output, Boolean Algebra, Gate-Level Minimization, Combinational Circuit Implementation, Truth Table-Based Implementation, Combinational Circuit Design.
COMBINATIONAL CIRCUIT BLOCKS: Adders in Verilog, Comparators in Verilog, Decoders in Verilog, Encoders in Verilog, Multiplexers in Verilog, Parity Generators and Checkers in Verilog, Applications on Combinational Circuits, Implementing the Home Alarm System, Implementing the Digital Safe System, Implementing the Car Park Occupied Slot Counting System, FPGA Building Blocks Used in Combinational Circuits.
DATA STORAGE ELEMENTS: Latches in Verilog, Flip-Flops in Verilog, Register, Memory, Read-Only Memory, ROM in Verilog, ROM Formation Using IP Blocks, Random Access Memory, Application on Data Storage Elements, FPGA Building Blocks Used in Data Storage Elements.
Digital system design using hdl Unit Four
SEQUENTIAL CIRCUITS
Sequential Circuit Analysis, State Table, State Diagram, State Representation in Verilog, Timing in Sequential Circuits, Synchronous Operation, Asynchronous Operation, Shift Register as a Sequential Circuit, Shift Registers in Verilog, Multiplication and Division Using Shift Registers, Counter as a Sequential Circuit, Synchronous Counter, Asynchronous Counter, Counters in Verilog, Frequency Division Using Counters, Sequential Circuit Design, Applications on Sequential Circuits.
Digital system design using hdl Unit Five
UNIT FIVE
Universal Asynchronous Receiver/Transmitter(UART) in Verilog, UART Applications, Serial Peripheral Interface (SPI) in Verilog, , SPI Application, Inter-Integrated Circuit (I2C) in Verilog, , I2C Application, Video Graphics Array (VGA) in Verilog, VGA Application, Universal Serial Bus (USB) Receiving Module in Verilog, USB Keyboard Application, Ethernet, FPGA Building Blocks Used in Digital Interfacing.
ADVANCED APPLICATIONS :Vending Machine, Digital Clock, Moving Wave via LEDs, Translator, Air Freshener Dispenser, Obstacle-Avoiding Tank, Intelligent Washing Machine, Non-Touch Paper Towel Dispenser, Car Parking Sensor System, Digital Table Tennis Game.
Digital system design using hdl Course Objectives
The main objectives of this course are:
Learn and understand the architectures of Field-programmable Gate Arrays.
Translate a software application into hardware logic for FPGA architectures.
Design synthesizable systems based on industry-standard coding methods.
Build testbenches and create data models to verify bit-true accurate designs.
Digital system design using hdl Course Outcomes
At the end of this course the student will be able to:
Understand the architecture of FPGAs, tools used in modelling of digital design.
Analyze and design basic digital circuits with combinatorial and sequential logic circuits using Verilog HDL.
Model complex digital systems at several levels of abstractions.
Design real time applications such as vending machine and washing machines etc.
Digital system design using hdl Text Books
1. CemUnsalan, Bora Tar “Digital System Design with FPGA Implementation Using Verilog and VHDL” McGraw-Hill Education, 2017
2. Design through Verilog HDL –T.R. Padmanabhan and B. Bala Tripura Sundari, WSE, IEEE Press, 2004.
Digital system design using hdl Reference Books
1. Advanced Digital Design with Verilog HDL –Michael D. Ciletti, PHI, 2005.
2. Fundamentals of Logic Design with Verilog –Stephen. Brown and Zvonko Vranesic, TMH, 2005.
3. A Verilog Primer –J. Bhasker, BSP, 2003.
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